The invention relates to an integrated circuit comprising a frequency divider having a symmetrical input which is intended to receive a signal having a first frequency, and a symmetrical output which is intended to receive a signal having a second frequency whose value is 2.N times lower than that of the first frequency, in which N is a predetermined integer which is at least equal to 2, the frequency divider being composed of memory cells realized in ECL technology, each having a symmetrical data input, a symmetrical clock input and a symmetrical data output.
An integrated circuit comprising a frequency divider is described in the article "Frequency dividers for ultra-high frequencies" by W. D. Kasperkovitz, published in Philips Technical Review 38 54-68, 1978/79 no. 2. This article describes the architecture of a memory cell realized in ECL technology, as well as a two-to-one divider using two of these memory cells. Each of these comprises a first and a second transistor constituting a first differential pair whose emitters are jointly connected to a negative power supply terminal via a current source, and whose bases constitute the symmetrical clock input of the memory cell. Each memory cell also comprises a third and a fourth transistor constituting a second differential pair, whose emitters are jointly connected to the collector of the first transistor, whose bases constitute the symmetrical data input of the memory cell and whose collectors are connected to a positive power supply terminal via load resistors. Each memory cell also comprises a fifth and a sixth transistor constituting a third differential pair, whose emitters are jointly connected to the collector of the second transistor, whose bases are connected to the collectors of the fourth and third transistors, respectively, and whose collectors are connected to the collectors of the third and fourth transistors, respectively.
The two-to-one divider described in this article comprises two of these memory cells. The data output of the first memory cell is connected to the data input of the second memory cell, the data output of the second memory cell being cross-connected to the data input of the first memory cell, the data output of the second memory cell constituting, in this embodiment, the output of the frequency divider circuit, the clock input of the first memory cell being connected to the input of the frequency divider circuit, the clock input of the second memory cell being cross-connected to said input. It is possible to use such a two-to-one divider for realizing a frequency divider circuit having a frequency division ratio number of 2.sup.M, in which M is an arbitrary integer, by cascade-arranging M two-to-one dividers conforming to the previously described structure, the first two-to-one divider receiving an input signal at its input, the output of each two-to-one divider being connected to the input of the subsequent two-to-one divider, except the output of the last two-to-one divider which constitutes the output of the frequency divider circuit. This structure has the advantage that it can function at very high frequencies, i.e. when the frequency of the input signal has, for example, GHz values. However, it has also major drawbacks. The differential pairs included in the memory cells of each two-to-one divider switch at each half cycle of the input signal. This results in the appearance of current peaks in the power supply terminals at each half cycle of the input signal of each two-to-one divider. These current peaks constitute noise, i.e. parasitic signals which propagate throughout the integrated circuit, because all of the components included therein are directly or indirectly connected to the power supply terminals. This noise has as many harmonics as there are cascade-arranged two-to-one dividers. Whereas certain harmonics only have little effect on the operation of the integrated circuit, others may be particularly detrimental. Finally, the structure described above does not allow a division by an even number which does not constitute a power of two.